1. Field of the Invention
This invention relates to electronic circuits, and more particularly, to an efficient method for a fast stabilizing output buffer.
2. Description of the Relevant Art
Very high-speed networks and computer buses continue to increase demand for bandwidth. By utilizing differential signaling, high-speed serial bus architectures are improving in order to satisfy this demand. Differential signaling electrically transmits information by means of two complementary signals sent on two separate wires. This technique can be used for both analog signaling, such as audio signal transmission, and digital signaling, such as within a Peripheral Component Interconnect (PCI) Express serial link interface and Universal Serial Bus (USB) interface.
One advantage of differential signaling includes a tolerance of ground potential differences between a transmitter and a receiver, since a receiver interface reads the difference between the two transmitted data signals and is not affected by the wires' voltages with respect to ground. Also, differential signaling is used with low voltages of mobile electronic devices since it provides twice the noise immunity of a single-ended system. Differential signaling helps to reduce the number of wire routes, or signal traces, and helps to reduce power consumption.
Differential signals are driven between a transmitter and a receiver by a differential amplifier, or differential driver, comprising a differential pair. If the input devices on a complementary metal oxide semiconductor (CMOS) differential pair are all nmos transistors, and the loads are either inductors or resistors, then a common-mode feedback buffer (CMFB), or loop or amplifier, is unnecessary. A CMFB is not required in this case, since the output resistance of this type of differential pair is weighted down by the low resistance of the inductor or resistors.
However, if a high-impedance transconductor, such as a nmos or a pmos transistor, is loaded with a high-impedance current source, such as a pmos or a nmos transistor, respectively, then a CMFB becomes necessary. Small differences between the bias current of the transconductor and the bias current of the load can induce large swings in voltage when multiplied by the high resistance of the output node.
In order to obtain a stable and predictable output signal, first, the CMFB needs to center the common mode output signal to a fixed but arbitrary chosen reference voltage. For maximal output voltage swing, a value that is half of the supply voltage is preferred. Second, the bandwidth of the CMFB has to be greater than the bandwidth of the differential amplifier. This requirement ensures the differential amplifier has a predictable and stable output response even with high frequency input signals. Third, the common mode input voltage range of the CMFB needs to be greater than the differential output range of the differential amplifier. And, fourth, the differential input range of the CMFB has to be greater than the differential output range of the differential amplifier.
Prior communication bus protocols utilizing Low Voltage Differential Signaling (LVDS) require an enabled CMFB to settle within hundreds of microseconds. Newer bus architectures utilizing similar techniques as LVDS require higher frequencies on the bus. Therefore, the CMFB is required to settle at a faster rate, such as a few nanoseconds, in order to maintain the corresponding differential data rate. This new settle time requirement for the CMFB is not met by current designs. The typical much slower settling times help eliminate signal stability problems. In order to maintain current circuit topologies, substantial power may need to be used to reach the new speeds. However, the bandwidth will be limited and stability issues arise with the unknown loads that can be coupled to the output.
In view of the above, efficient methods and systems for a fast stabilizing output buffer are desired.